1. Field of the Invention
The present invention relates to silicon-on-insulator semiconductor devices, and more particularly to a quasi surrounding gate and a method of fabricating a SOI semiconductor device with the same to increase the current per device unit length and allows better control over short-channel effects.
2. Description of the Prior Art
The active element common to many microelectronic circuits is the SOI metal-oxide-semiconductor field-effect transistors (MOSFETs). A conventional MOSFET operates by driving current through the channel region between the source and drain of the device. The conductivity of the channel region is modulated by the application of a voltage on the conducting gate above the channel surfaces and insulated from it. Efforts are ongoing within many MOS integrated circuit manufacturing companies as well as laboratories to improve the speed and available drive current of the SOI MOSFET, to improve its reliability and reduce its power consumption.
SOI is the generic term describing those technologies in which the MOSFETs or other active devices are built in a thin film of silicon over an insulating layer or substrate. The presence of the insulator reduces the parasitic capacitance in the MOSFET compared to a bulk silicon device, resulting in inherent improvements in the speed and power dissipation of MOS integrated circuits, as well as improved immunity to single-event upset of MOS memory elements in a radiation environment.
Present MOS transistors drive current flow in a surface-inversion layer, such as shown in FIG. 1. In between a source area 11 and a drain area 12 at the ends of the channel, the surface-inversion layer 14 formed within serves as a pathway to drive the current when a voltage is applied at gate 13.
However, due to the limited current available in a surface inversion-layer at the top silicon interface of a MOS transistor, improvement is essential to be able to provide better performance and at the same time, being able to prevent short-channel effect, drain-induced barrier lowering and sub-threshold slope degradation.
In view of the above problems, the invention seeks to provide a quasi surrounding gate MOSFET.
Another object of the invention is to provide a quasi surrounding gate MOSFET having an improved current drive and transconductance.
Another object of the invention is to form a quasi surrounding gate MOSFET using Silicon On Insulator wafer.
Yet another object of the invention is to provide a method for fabricating a quasi surrounding gate by volume-inversion on an SOI wafer. The so called volume-inversion means that inversion is not only observed in a surface channel at the top interface of the semiconductor, but inside the volume of the semiconductor layer and at along its sides.
Still another object of the invention is to fabricate a quasi surrounding gate structure with better control over short-channel effects and sub-threshold leakage.
The invention takes advantage of SOI wafers, bulk silicon wafers and conventional processing techniques using new methods to form a novel quasi surrounding gate MOSFET structure. The method for forming a quasi surrounding gate MOSFET described herein employs conventional MOS processing steps in combination with well-established SOI techniques. Therefore, the invention enables the forming of a semiconductor device with a quasi surrounding gate to be manufactured using only established process techniques, that have been used in the past to construct bulk or SOI MOSFETs.
According to an embodiment of the invention, the steps of fabricating a silicon-on-insulator semiconductor device with quasi surrounding gate, comprising:
(a). forming a semiconductor layer on a semiconductor substrate via a first insulation layer;
(b). forming an first oxide layer on the semiconductor layer;
(c). forming a sacrificial nitride layer on the oxide layer;
(d). patterning the layers of the semiconductor, the oxide and the sacrificial nitride into an island or a strip by a lithographic process;
(e). forming a second oxide layer around the semiconductor layer;
(f). stripping the sacrificial nitride layer;
(g). depositing a second sacrificial nitride layer along the semiconductor layer;
(h). using the second sacrificial nitride layer as a mask and etching the first insulation layer to a depth;
(i). forming dielectric material around the island or the strip of the semiconductor layer;
(j). using the second sacrificial nitride layer as a mask and depositing polysilicon;
(k). removing the second sacrificial nitride layer; and
(l). forming source and drain regions in the semiconductor layer by implanting doping ions whose conductivity type is opposite to that of the semiconductor substrate, using the gate electrode as a mask.
The structure of the quasi surrounding gate of the invention, such as FIG. 2, mainly comprises a first insulating layer 21; a submicron-thick semiconductor layer 22 on the first insulating layer 21, the semiconductor layer 22 having a generally intrinsic bulk channel region; a gate insulating layer 23 surrounding the semiconductor layer; and a gate 24, almost enclosing the gate insulating layer fully.
As shown in FIG. 3, 31 represents a first insulating layer, 32 represents a semiconductor layer, 33 represents a gate insulating layer, and 34 represents a gate.